As it is known in the art, a computer processing system generally includes a computer processor for executing an instruction stream which is stored on a memory or a disk. A variety of software applications may be executed simultaneously by the computer processing system. One of these applications controls the images which are displayed on a monitor coupled to the computer processing system. The computer processing system often includes specialized graphics hardware and software to control the image information that is displayed on the monitor.
Graphics hardware typically includes a graphics controller and a video frame buffer. The graphics controller receives commands from the computer processing system to control the manipulation of data within the frame buffer. The graphics controller may include logic to increase the performance of a variety of graphics functions such as copying data from memory to the frame buffer, drawing lines, or stippling data.
The graphics controller provides an address and data to the video frame buffer. The data is provided in the form of binary pixels, where each pixel comprises color or intensity information. For example, in a gray-scale system, a pixel may comprise one byte of intensity data which would distinguish 2.sup.8 (256) different shades of gray ranging from black to white.
Each monitor has defined display dimensions for the number of vertical and horizontal pixels which are displayed on the screen of the monitor. Each row of horizontal pixels which are displayed is referred to as a `scan line`. The width of the display is determined by the number of pixels in the scan line, and the height of the display is defined by the number of scan lines in the image.
The frame buffer is generally comprised of Dynamic Rams (DRAMS) or videoRAMs, where each videoRAM has both a random access memory (RAM) device and a shift register. During normal operation, rows of videoRAM data are repeatedly transferred to the shift register. The output of the shift register provides a constant serial stream of pixels to a digital to analog converter which in turn provides a constant stream of analog pixel data to the monitor.
When the computer processor performs a graphics operation, it updates the pixel data in the videoRAMS. The updated data is displayed on the screen the next time the pixel data is shifted out of the shift register. Graphics performance is typically measured by how fast the graphics controller can update data in the videoRAMs.
One graphics operation which typically has low performance compared to other types of operations is line drawing. Non-horizontal lines are slow due to the traditional organization of video frame buffer memory. Traditionally, video memory is organized such that a pixel of one scan line is stored in the same videoRAM device as the same pixel in the next adjacent scan line. As a result, when a non-horizontal line crosses scanlines, successive pixels of the line may be written to different addresses in the same RAM device. Vertical lines, in particular, are the worst case in terms of performance because all pixels of the line are written to the same videoRAM device. Successive writes to the same videoRAM device are undesirable because the writes cannot be performed in parallel, but must be performed sequentially and thereby reduce graphics performance.
For example, referring now to FIG. 1, an example arrangement of a video memory 10 is shown to store a plurality of 32 pixel scan lines 12a-12k, where each pixel is designated by its pixel location in the scan line. An operation to draw a vertical line on the display may alter color data in pixel 10 of each scan line 12a-12k as shown in FIG. 1, where the altered pixels of the vertical line are shown as outlined group 13.
A video bus 16 is a 64 bit bus coupled to transfer data to and from video memory 10. Providing 64 bits of write data per memory cycle increases the performance of the graphics processor by increasing the number of pixels in video RAM which can be altered during one memory transaction.
However, it is noted that in the prior art layout shown in FIG. 1, because each pixel of the vertical line is stored in the same videoRAM device, a separate memory transaction must occur for each pixel of the vertical line. These memory transactions cannot occur in parallel, but must be performed sequentially. As a result, only 8 bits of the 64 bit bus are used to carry pixel information, while the remaining portion of the bus is unused.
It would be desirable to identify a simple method for increasing the performance of non-horizontal line drawing without impacting the performance of other modes of graphics operations.